{"id":915491,"date":"2026-06-26T03:12:04","date_gmt":"2026-06-26T08:12:04","guid":{"rendered":"https:\/\/newsycanuse.com\/index.php\/2026\/06\/26\/ibm-has-unveiled-chip-technology-that-could-help-extend-moores-law-another-decade\/"},"modified":"2026-06-26T03:12:04","modified_gmt":"2026-06-26T08:12:04","slug":"ibm-has-unveiled-chip-technology-that-could-help-extend-moores-law-another-decade","status":"publish","type":"post","link":"https:\/\/newsycanuse.com\/index.php\/2026\/06\/26\/ibm-has-unveiled-chip-technology-that-could-help-extend-moores-law-another-decade\/","title":{"rendered":"IBM has unveiled chip technology that could help extend Moore\u2019s Law another decade"},"content":{"rendered":"
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IBM has built a new prototype chip with around 100 billion transistors on an area the size of a fingernail, which is twice the density of the company\u2019s previous state-of-the-art technology announced in 2021. The design could pave the way for faster and more energy efficient computers for years to come.<\/p>\n

For more than half a century, chipmakers have been able to make ever more powerful computers by following the key principle of Moore\u2019s Law: Cram more transistors onto the chip. To do this, they shrank transistors\u2014the tiny switches that perform computations\u2014to incrementally smaller sizes. But in the last 15 years, transistors have gotten close to the point where quantum mechanics starts to interfere with their function: just a few dozen nanometers in size. They can\u2019t get smaller.<\/p>\n<\/p><\/div>\n

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So to fit more transistors on a chip, engineers across the industry are eyeing a pivot to an approach familiar to urban planners: build up. On Thursday, IBM announced it has created a chip that uses this strategy. The new architecture, known as a nanostack, vertically stacks transistors in two layers on a silicon chip.<\/p>\n<\/div>\n

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\u201cIt\u2019s not just an incremental step,\u201d Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. \u201cIt\u2019s a meaningful leap forward.\u201d Within a decade, Gambetta expects, chips with nanostacking will be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption.<\/p>\n

\u201cAbsolutely, it\u2019s transformational,\u201d says Dan Hutcheson, vice chair of TechInsights, a technology analysis company. \u201cThis puts another 10, 15 years on the roadmap.\u201d\u00a0<\/p>\n

Compared with IBM\u2019s previous state-of-the-art architecture, the company reports, chips built with this new approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient.\u00a0<\/p>\n

The architecture offers a general way of laying out transistors, and IBM will partner with semiconductor manufacturers to make the actual chips. It anticipates that chip designers will deploy the design in many different types of chips, including GPUs and CPUs. \u201cI expect to have many conversations with designers about how they can use this technology,\u201d Huiming Bu, IBM\u2019s vice president of global semiconductor R&D, said in the press conference announcing the new design.\u00a0<\/p>\n

A layer cake<\/strong><\/h3>\n

Engineers created IBM\u2019s new chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon. Then they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors. This kind of vertical stack, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET, explains Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work.\u00a0<\/p>\n

The company isn\u2019t the only one pursuing this general approach. The biggest chip manufacturers\u2014Intel, Samsung, and TSMC\u2014and the competing research lab Imec in Belgium have been investigating CFETs<\/a>. IBM says its design is distinguished by the fact that the transistors in the second layer do not sit directly on top of the first layer\u2019s transistors; rather, they are staggered, which the company says simplifies wiring, among other advantages.\u00a0<\/p>\n

CFETs like those in IBM\u2019s nanostack architecture contrast with another common approach to making two-tiered chips, such as AMD\u2019s 3D V-Cache and Huawei\u2019s forthcoming LogicFolding technology, Cao says. In those approaches, engineers fabricate the transistors on each layer of the chip independently before bonding the two together. IBM\u2019s new method allows for more precise alignment of the layers, which is important for performance because transistors are so tiny, says Cao.\u00a0<\/p>\n<\/p><\/div>\n

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Nanostacking builds on an approach called nanosheet technology, which has been used to make current state-of-the-art transistors since around 2022. A transistor is essentially a hose through which electrons flow, with a valve that can turn the flow on or off. Inside the transistor, electrons move through a patch of the silicon called a channel. In IBM\u2019s nanostack approach, the channel consists of three nanosheets that are each 15 atoms thick, spaced nine nanometers apart.\u00a0<\/p>\n<\/div>\n

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Every chip generation gets a name. IBM refers to its nanostack technology as \u201csub-nanometer\u201d or \u201c0.7 nanometer,\u201d following a longtime industry convention where each generation is named for a smaller and smaller length. But \u201c0.7 nanometer\u201d is a marketing term and does not correspond to any physical characteristics of the chip. The distance between transistors \u201chas been staying at about 40 nanometers for quite a long period of time,\u201d says Cao.\u00a0<\/p>\n

Putting it into production<\/strong><\/h3>\n

Looking ahead, chipmakers can try increasing transistor density by building on more tiers, as Bu suggested in the press conference. However, they will face practical challenges, according to Cao. Manufacturing introduces errors, which means a certain number of chips are faulty upon creation. \u201cHere you\u2019re building another layer on top, so if either top layer or bottom layer fail, your entire chip is going to fail,\u201d says Cao. The resulting failure rate will be higher than for single-layer chips, and that will be costly.<\/p>\n

Another central challenge is what Cao calls \u201cthe thermal budget.\u201d Essentially, it means that engineers need to figure out how to build each layer without melting the connections to the one underneath. This means keeping manufacturing processes below 400 \u00b0C. IBM figured out how to make the second stack at low enough temperature, although the company is mum about its methods.\u00a0<\/p>\n

Academics are also on the case. Cao\u2019s group, for example, has created a method for stacking transistors<\/a> layer by layer where the second layer is created with processes below 200 \u00b0C. They manage this by using a type of transistor known as the junctionless transistor, which can be created without a typically required step called doping\u2014a process that injects non-silicon atoms into silicon to tune the material\u2019s properties. Doping is usually the hottest part of fabricating transistors. Cao thinks from a thermal management perspective, his approach could be easier to scale up to multiple tiers, although his demonstration is just a proof of principle.<\/p>\n

But Cao thinks IBM\u2019s work is \u201ctransformative\u201d because it demonstrates how to stack transistors \u201con a full wafer using a state\u2011of\u2011the\u2011art manufacturing line.\u201d The new approach pushes the industry forward, he says: \u201cI\u2019m interested in what\u2019s their killer application.\u201d <\/p>\n<\/div>\n

Read More<\/a>
\n Sophia Chen<\/p>\n","protected":false},"excerpt":{"rendered":"

IBM has built a new prototype chip with around 100 billion transistors on an area the size of a fingernail, which is twice the density of the company\u2019s previous state-of-the-art technology announced in 2021. The design could pave the way for faster and more energy efficient computers for years to come. For more than half<\/p>\n","protected":false},"author":1,"featured_media":915492,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[46,2834],"tags":[],"class_list":["post-915491","post","type-post","status-publish","format-standard","has-post-thumbnail","category-technology","category-unveiled"],"aioseo_notices":[],"_links":{"self":[{"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/posts\/915491","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/comments?post=915491"}],"version-history":[{"count":0,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/posts\/915491\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/media\/915492"}],"wp:attachment":[{"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/media?parent=915491"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/categories?post=915491"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/newsycanuse.com\/index.php\/wp-json\/wp\/v2\/tags?post=915491"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}