Analyst Ming-Chi Kuo says the new CoPoS technology could make AI chips cheaper and more powerful.
Making chips smaller has dominated the semiconductor conversation for years, but TSMC’s next big leap may come from how those chips are packaged instead. According to analyst Ming-Chi Kuo, the company is developing a new Chip-on-Panel-on-Substrate, or CoPoS, technology that promises lower manufacturing costs while delivering better performance for future AI processors.
TSMC’s CoPoS packaging could make future AI chips both cheaper and faster
In a recent post on X, Ming-Chi Kuo revealed that TSMC is working on CoPoS, an advanced packaging architecture that replaces conventional wafer-based manufacturing with panel-level processing. The shift to rectangular panels allows for better material utilization and supports significantly larger package sizes, making it particularly attractive for increasingly complex AI accelerators. Furthermore, reports suggest the technology could enter mass production around 2028.
Key takeaways on TSMC’s next-generation advanced packaging, CoPoS (publicly available technical details omitted):
1. CoPoS is currently expected to enter mass production in 2H28. It is designed to improve the economics of ultra-large packages above the 9.5x reticle-size class,…
— 郭明錤｜Ming-Chi Kuo (@mingchikuo) June 11, 2026
Kuo also clarified that, contrary to some early interpretations, glass is only used as a temporary carrier during manufacturing rather than becoming part of the finished package itself. The final substrate remains conventional, while the new process aims to reduce waste and improve production efficiency without sacrificing performance.
The technology is expected to complement TSMC’s existing CoWoS packaging rather than replace it outright. Reports have also floated NVIDIA’s future Feynman AI chips as potential early adopters, given the industry’s growing demand for ever-larger AI packages packed with compute chiplets and high-bandwidth memory.
Turns out the biggest innovation might not be inside the chip
The funny thing is that transistor shrinks are no longer the only way to chase performance gains. As AI models demand more memory, more compute, and more bandwidth, advanced packaging has quietly become one of the semiconductor industry’s hottest battlegrounds, with companies looking for smarter ways to stitch everything together.
If CoPoS delivers on its promise, it could help reduce production costs while enabling even larger and more capable AI processors. That might not sound as flashy as a new 2nm process node, but in today’s AI race, how you package a chip is rapidly becoming just as important as how you manufacture it
Varun is an experienced technology journalist and editor with over eight years in consumer tech media. His work spans…
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